FPGA based Acceleration for Financial Trading

Our FPGA-based smart feed handlers enable the acceleration of financial trading platforms, and are especially aimed at high-frequency trading, ultra-low latency feed handling, and real-time algorithmic trading.

The following diagrams illustrate two possible use models for our 'Ticker Plant' acceleration platforms.

FPGA Trading System 1 FPGA Trading System 2
Fig. 1 - FPGA based trading architecture #1 Fig. 2 - FPGA based trading architecture #2

Our smart feed handlers' solution framework includes a combination of hardware, firmware, and software, each provided with different options to fit specific acceleration requirements.

» Hardware platforms

We currently offer the following FPGA hardware platforms that are designed specifically for low-latency trading.


XP4S530LP-20G XP4S1050GT-20G XP4S1050-10G XP6V550-2G
XP4S530LP-20G XP4S1050GT-20G XP4S1050-10G XP6V550-2G
Quick facts:
- Low profile PCIe 2.0 (Gen2) x8
- Dual 10G or dual 1G Ethernet
- 2GB DDR3 SDRAM
- 36MB QDRII+ SRAM		 Quick facts:
- Dual FPGA
- PCIe 2.0 (Gen2) x8
- Dual 10G Ethernet
- 1GB DDR3 SDRAM		 Quick facts:
- Dual FPGA
- PCIe 2.0 (Gen2) x4
- 10G Ethernet
- 1GB DDR3 SDRAM		 Quick facts:
- PCIe 2.0 (Gen2) x8
- Dual 1G Ethernet
- 8GB DDR2 SDRAM
- 18MB QDRII+ SRAM
details » details » details » details »

» Firmware environment

We offer a complete IP infrastructure that enables near instant access to market data, with 70ns Ethernet MAC latency, 200ns Ethernet MAC + TOE latency, and under 50ns PCI Express + DMA latency at Gen2 and Gen3 speeds.


Framework #1:
- 10G or 1G Ethernet MAC
- PCIe multi-channel DMA controller
- Memory controllers

Framework #2:
- 10G or 1G Ethernet MAC
- 10G or 1G Traffic Offload Engine (TOE)
   (Up to 32 sessions)
- PCIe multi-channel DMA controller
- Memory controllers

IP infrastructure for feed handling

» Infrastructure software


PCIe driver & software layers

Our solution includes a latency optimized PCIe device driver for 32-bit and 64-bit Linux distributions. A C/C++ API provides application software with easy to use higher-level functions to access hardware resources.

A FPGA Flash Configuration module enables seamless configuration of the FPGA FlashPROM through the PCIe interface. This mechanism greatly simplifies field updates of the FPGA firmware.

» Productivity software

Our Hardware Compile Environment "HCE" allows compilation of algorithmic C into FPGA hardware. HCE is a hardware-aware compiler optimized for our range of FPGA accelerator cards. HCE automatically generates the interfaces and control logic that enables HCE-compiled algorithms to connect seamlessly with the FPGA's IP infrastructure.

 HCE within MS Visual C++

» Documentation

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Solution brochure 1.0 927 KB