Gael is a seasoned entrepreneur, and a recognized innovator with 24 years of experience in EDA & semiconductors. Prior to leading the Accelize team, Gael was CTO of the QuickPlay Business Unit at PLDA; Vice President Software Engineering at Achronix; R&D Director of FPGA Synthesis Products at Synplicity; and ASIC & FPGA designer at Cadence. Gael authored or co-authored 26 patents in the field of high-level synthesis, logic synthesis, optimizations and asynchronous circuits. Gael is also the inventor of the RTL Encryption scheme that became the widely used IEEE 1735 standard.